FIG. 1 illustrates in block diagram form a microprocessor 10 coupled to memory device 12 via a data bus 14. Although not shown, data bus 14 includes a plurality of conductive lines, each one of which is capable of transmitting a data bit signal between memory device 12 and microprocessor 10.
Microprocessor 10 includes a plurality of input/output (IO) devices (not shown in FIG. 1) coupled to respective conductive lines of data bus 14. IO devices transmit or receive data bit signals. FIG. 2 is a schematic diagram of a driver 16 contained in one of the IO devices of microprocessor 10. Driver 16 drives one of the conductive lines of data bus 14 in response to receiving an input data bit signal.
Driver 16 includes a p-channel field effect transistor 20, an n-channel field effect transistor 22, an input node 24, and an output node 26. Although not shown, output node 26 is coupled to a conductive line of data bus 14. P-channel field effect transistors will be referred to as p-channel FETs, and n-channel field effect transistors will be referred to as n-channel FETs. N-channel and p-channel FETs include a gate, a drain, and a source designated g, d, and s, respectively. The gates of FETs 20 and 22 are coupled to input node 24. The drains of FETs 20 and 22 are coupled to output node 26. The source of FET 20 is coupled to Vdd, while the source of FET 22 is coupled to Vcg. Vdd is a supply voltage provided from a source external to microprocessor 12, while Vcg is common ground.
In operation, input node 24 receives an input data bit signal Din directly or indirectly from the core of microprocessor 10. Although not shown, Din is typically provided to input node 24 by a signal inverting circuit. The input data bit signal Din varies between two voltage levels Vdd or Vcg representing a binary one or a binary zero, respectively. In response to receiving Din, driver 16 chargers or discharges output node 26 and the conductive line of data bus 14 coupled thereto. When driver 16 receives Din equal to Vcg, driver 16 charges output node 26 to Vdd. When driver 16 receives Din equal to Vdd, driver 16 discharges output node 26 to Vcg. In this manner, driver 16 generates an output data bit signal Dout at output node 26 that varies between Vdd and Vcg in response to receiving input data bit signal Din that varies between Vdd and Vcg.
P-channel or n-channel FETs are often referred to as electronic switches. A p-channel FET is active or xe2x80x9cswitched onxe2x80x9d when its gate voltage Vg is a threshold voltage Vt or more below its source voltage Vs. In other words, a p-channel FET is active when Vg less than Vsxe2x88x92Vt. When active, a p-channel FET provides a very low impedance path between its source and drain such that current can flow therebetween. When its gate voltage Vg is greater than a threshold voltage Vt below its source voltage Vs the p-channel FET is inactive. In other words, a p-channel FET is inactive when Vg greater than Vsxe2x88x92Vt. When inactive, essentially no current can flow between the p-channel FET""s source and drain. In FIG. 2, p-channel FET 20 is active when the voltage of Din is Vcg and inactive when Din is Vdd.
An n-channel FET is active or xe2x80x9cswitched onxe2x80x9d when its gate voltage Vg is a threshold voltage Vt or more above its source voltage Vs. In other words, an n-channel FET is active when Vg greater than Vs+Vt. When active, an n-channel FET provides a very low impedance path between its source and drain such that current can flow therebetween. An n-channel FET is inactive when Vg less than Vs+Vt. When inactive, essentially no current can flow between the n-channel FET""s source and drain. In FIG. 2, n-channel FET 22 is active when the voltage of Din is Vdd and inactive when Din is Vcg.
N-channel or p-channel FET operation is subject to limitations. More particularly, the voltage Vgd between the gate and the drain of the devices or the voltage Vgs between the gate and source of the devices should not exceed a gate oxide voltage limit Vlimit. If Vgs or Vgd exceeds Vlimit in either a p-channel or n-channel FET, damage can occur to the FET that renders it permanently inoperable.
Vlimit (also known as gate oxide integrity) depends on failure in time (FIT) rate, the gate area of the FET, and/or the distance between the source and drain of the FET. The FIT rate requirement is provided by a system design specification. For p-channel and n-channel FETs manufactured using a 0.18 micron process, Vlimit may vary between 1.4-1.8 volts depending on how the p-channel FETs are operated. The Vlimit for p-channel and n-channel FETs of a particular size and used in a particular manner, can be determined based on experimental results.
The sizes of FETs, including the distance between sources and drains thereof, in microprocessors continue to reduce as semiconductor manufacturing technology advances. As FETs continue to reduce in size, so does their Vlimit.
As noted above, driver 16 operates to charge or discharge output node 26, and thus the conductive line of data bus 14 and the memory device 12 coupled thereto, in accordance with the input data bit signal Din. Characteristics of driver 16 are subject to variations in operational parameters such as temperature and/or magnitude of supply voltage Vdd. For example, an increase in operating temperature of driver 16 may increase its output impedance and potentially reduce driver 16""s drive strength or ability to fully charge or discharge output node 26 within a predetermined amount of time.
Notwithstanding variations in operational parameters, which are dynamic in nature, the actual output impedance of driver 16 may not match the expected impedance of driver 16 due to unexpected and permanent variations in the physical structure of FETs 20 and 22. More particularly, microprocessors including their drivers are manufactured on silicon wafers using complex equipment and processes. Once completed, the microprocessors are severed from the silicon wafer and individually packaged for subsequent use. A single wafer, depending on its size, is capable of producing several microprocessors. In theory, each of these microprocessors should be identical to each other in physical structure. In practice, slight physical variations exist between these microprocessors. For example, due to variations in the fabrication process, the doping density in the source or drain regions of FETs 20 and 22 of driver 16, or the length or width of gates of FETs 20 and 22 of driver 16, may unexpectedly vary from microprocessor to microprocessor. These physical variations in the FETs are static in nature and may unexpectedly increase or decrease the output impedance of driver 16.
Generally, the output impedance of driver 16 can be represented as its output voltage V divided by its output current I. As noted above, the output impedance of driver 16 may vary with, for example, temperature and/or magnitude of Vdd. FIG. 4 illustrates IV curves that plot the output voltage V of driver 16 versus the output current I of driver 16. Each IV curve corresponds to driver 16 operating at different temperatures and/or magnitudes of Vdd. The IV curves of FIG. 4 were drawn with the presumption that no load is applied to output node 26.
As can be seen from FIG. 4, each of the IV curves are non-linear which means that the output impedance of driver 16 varies with its output voltage. The IV curves of FIG. 4 also show that output impedance of driver 16 varies with temperature and/or magnitude of Vdd for a given output voltage V. The impedance of the conductive line and the memory device 12 coupled to output node 26, however, is static or substantially static. As a consequence, a mismatch generally occurs between the output impedance of driver 16 and the combined impedance of the conductive line and memory device 12. This mismatch of impedances may degrade or limit the ability of driver 16 to transmit data bit signals to memory device 12 for storage therein.
As noted above, driver 16 charges or discharges output node 26, and thus the conductive line of data bus 14 and the memory device 12 coupled thereto, in accordance with the input data bit signal Din. A timing specification for data bus 14 may require driver 16 to fully charge or discharge output node 26 during predefined timing windows in order to properly transmit data bit signals to memory device 12. Microprocessor 10 including its drivers 16 should be designed to meet the timing requirements of data bus 14. The design should take into account expected transmission delays of driver 16 and other circuitry coupled to input node 24. Unfortunately, the actual transmission delays of driver 16 and other circuitry coupled to input node 24 do not always equal the expected transmission delays due to variations of microprocessor temperature and/or the magnitude of supply voltage Vdd. These variations may inhibit the ability of driver 16 to fully charge or discharge node 26 during the timing windows required by the specification of bus 14. To illustrate, an increase in temperature beyond that which is expected, may slow the driver 16""s ability to fully charge or discharge output node 26 such that driver 16 cannot charge or discharge output node 26 to Vdd or Vcg, respectively, during predefined timing windows.
Notwithstanding variations in temperature and magnitude of supply voltage Vdd, the actual ability of driver 16 to fully charge or discharge output node 26 during predefined timing windows may also be affected by unexpected variations in the physical structure of FETs of microprocessor 10 including FETs 20 and 22. These physical variations in the FETs may unexpectedly increase or decrease the ability of driver 16 to charge or discharge output node 26 during predefined timing windows.
Disclosed is an input/output (IO) device for transmitting a data bit signal. In one embodiment, the IO device includes an IO device input node for receiving an input data bit signal, an IO device output node, and a common ground node. The IO device also includes a first driver having first and second n-channel FETs coupled together, first and second p-channel FETs coupled together, a plurality of third n-channel FETs each having a drain coupled to the IO device input node, and a plurality of first capacitors coupled between the common ground node and respective sources of the plurality of third n-channel FETs. The drains of the first p-channel FET and the second n-channel FET are coupled to the IO device output node, while the gate of the first n-channel FET is coupled to the IO device input node.
In another embodiment, the IO device includes a plurality of fourth n-channel FETs each having a drain coupled to the IO device input node, and a plurality of second capacitors coupled between the common ground and respective sources of the plurality of fourth n-channel FETs. In this embodiment, IO device also includes a first code generation circuit for generating a first code, and a second code generation circuit for generating a second code. The first and second codes are defined by a plurality of first code bit signals and a plurality of second code bit signals, respectively. Each of the plurality of third n-channel FETs includes a gate that receives a respective first code bit signal from the first code generation circuit, while each of the plurality of forth n-channel FETs includes a gate coupled that receives a respective second code bit signal from the second code generation circuit.